Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA ...
Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
EDN

Perl shines in testbenches

Vera, “e,” Rave, Testbuilder, Cynlib-there are many specialized languages that can speed testbench development for HDL simulation. A small, quiet EDA company, GreenLight LLC, has another idea: Why not ...